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During measurements around the MPC565MZP56 I got an unexpected behaviour of the RD/WR-signal: Following conditions: - RD/WR is configured with internal pull-up ("SPRDS"_bit is reset in the PDMCR-register) - a "normal" write is performed with no wait-states, no TRLX-Bit, no EHTR, no CSNT Following unexpected behaviour: - after the write access, the RD/WR-signal is "floating" over several clock-cycles until it reaches the 2,6V - "floating" means: it seems that the RD/WR-signal is charged through the internal pull-up-resistor until it has reached the 2,6V-I/O-voltage - due to this "floating"-behaviour the RD/WR-signal goes through the undefined range (between Input-LOW and Input-HIGH) of the inputs of the connected digital logic (e.g. RD/WR-Input of the SRAM). It seems that the RD/WR signal is only driven (e.g. driven to '0' during a write access) when the driver is enabled. This results in the behaviour that the RD/WR-signal is driven low for e.g. 2 clock-cycles (during a write access without wait-states) and after the 2 clock-cycles the RD/WR-signal is not driven anymore. After the write access the RD/WR-signal is rising very slow to 2,6V (depending on the pull-up-resistor and the capacity at this pin). This behaviour is shown in the attached screen-shot from an oscilloscope: - clk_n_cs_rnw_open.jpg (channel1 = Clock, channel2 = N_CS, channel3 = RD/WR) - clk_n_cs_rnw_open_1.jpg In comparison the N_TS-signal was also measured. The signal N_TS does not show this behaviour: - clk_n_cs_nts_open_1.jpg (channel1 = Clock, channel2 = N_CS, channel3 = N_TS) clk_n_cs_rnw_open.jpg clk_n_cs_rnw_open_1.jpg clk_n_cs_nts_open_1.jpg Message Edited by t.dowe on 2009-11-08 10:28 PM
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